This invention relates to a digital circuitry and logic design. In particular, the present invention provides a long setup flip-flop with improved synchronization and metastability resolving capabilities.
In the communication between digital subsystems that do not share a common time reference, signals may occur which are not stable. When this occurs a problem condition may arise where resolution to a logically defined state within a bounded period of time does not occur. The inability for a digital circuit to settle within a bounded period of time is commonly referred to as metastability and may lead to processing errors if not properly synchronized.
Metastability is an increasingly significant problem for digital circuit design, particularly as clock rates increase. In addition to posing potential disorders in asynchronous systems, metastability can be a problem in synchronous systems where the data input is not kept stable during the setup and hold-time constraints of a flip-flop.
A flip-flop is a bistable device, i.e. it has two stable states: xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d (also referred to as xe2x80x9clowxe2x80x9d and xe2x80x9chighxe2x80x9d). Under certain conditions, the flip-flop may enter a metastable state where node voltages remain near the threshold level. In this case, node voltages may not resolve to a logically defined state and where they may remain so for an indeterminate amount of time.
In particular, a metastable state may be induced in an edged-triggered device, for example, with the simultaneous arrival of data during a sampling period. In an edge-triggered device, the input data signal is captured only during the very short time when the clock is changing (i.e. during the xe2x80x9cedgexe2x80x9d of the clock pulse). If the input signal changes during a clock edge it is possible to enter a metastable condition. In this instance, the flip-flop device may become unable to resolve to either a 0 or a 1 thereby requiring a prolonged period waiting period for the metastability to resolve. Typically, noise (switching and/or thermal) or a slight imbalance eventually causes resolution to occur. However, prior to resolution of this imbalance, the interpretation of the metastable signal may cause a synchronization failure where the undefined value is sampled by other digital circuitry and propagates through the system causing system failures and/or malfunctions.
Once the flip-flop enters a metastable state, the probability that it will remain metastable some time later has been shown to be an exponentially decreasing function which determines the mean time between failure (MTBF):   MTBF  =            ⅇ              t                  τ          r                                    T        w            ⁢              f        c            ⁢              f        d            
where t is the time by which the device must be resolved (the metastability settling time), xcfx84r is the exponential decay rate indicating how long a device is expected to remain in a metastable state once placed there (the metastability time resolution constant), Tw is the likelihood of entering a metastable state (window of metastability propensity), fc is the frequency of the clock, and fd is the frequency of the data. It is desirable to maximize MTBF. This becomes increasingly difficult as the clock frequency fc increases.
In order to reduce the problems caused by metastability and thereby improve MTBF, circuits called synchronizers are utilized to resolve the undefined signal to be either in the low or high state before it is sampled by other digital circuitry. Typically, synchronizers utilize a latching element that holds data while metastabilities are being resolved. Often synchronizers utilize two cross-coupled CMOS inverters back-to-back, as depicted in circuit 1000 of FIG. 1, which employ a regenerative configuration with positive feedback to capture and retain the input data. Such an arrangement allows a whole clock cycle to resolve metastability. Multiple synchronizers may be cascaded to improve the metastability resolving characteristics of the circuit but at the cost of increased latency, i.e. a full clock period of latency for each additional synchronizer.